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ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com overview features block diagram ? integrates all required components for a complete avi or atapi interface dvd drive (front-end) electronics solution: -rf amp - data channel - servo control processor - dvd ecc (error correction code) - css (content scramble system) - atapi decoder reads dvd+rw, dvd-rom, dvd-rw, cdda, cd- rom, cd-r, cd-rw, vcd, and dvcd discs direct audio/video interface for dvd player applications atapi interface for game console and dvd loader solutions high-performance controller supports dvd disc speeds up to 8x and cd-rom disc speeds up to 40x partial response maximum likelihood (prml) data channel servo control processor (scp) on-chip dvd navigation support 208-pin lqfp/epad packages the CL-CS3712 is cirrus logic?s high-integration, high- performance atapi dvd drive manager. it integrates all required components for a dvd loader for dvd players, game consoles, and dvd-rom drives. the CL-CS3712 includes an rf amp, servo control processor, data channel, dvd ecc, css authorization, cd-rom decoder, and atapi interface. the CL-CS3712 can be configured with an audio dac (digital-to-analog converter), external buffer memory (8- or 16-bit dram), a local micro-controller with its ram and rom, and power drivers to create a complete dvd-rom electronics solution. the CL-CS3712 supports dvd disc speeds up to 8x and ultra dma host speeds up to 33.3 mbytes/sec. the rf signal is over-sampled by a high-speed adc (analog-to-digital converter). the timing loop is closed in the digital domain with variable decimation and interpolation used to provide the output samples to the data recovery logic. a channel-quality logic circuit is provided to allow parametric calibration. the CL-CS3712 data channel supports partial response maximum likelihood (prml) data acquisition, providing state-of-the-art data recognition in a noisy environment, coming from the pick-up head. CL-CS3712 to power drivers from sensors local microcontroller ata pi o r mpeg sample rate gen spindle control host interface layered ecc & dvd ecc c1/c2 ecc & de-interleave 8/16 demod efm demod buffer memory channel quality bac capture from iv amp dpll & data chnl rf adc low pass filter sum & vga dacs vga adcs scp synthesizer ram sub-q read header search & checks buffer manager css authentification navigation css descramble subcode de-interleave CL-CS3712 micro interface integrated avi/atapi dvd drive manager datasheet
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com features (cont.) overview (cont.) rf amp provides laser power control gain control in digital domain generates focus error and tracking signal provides rf signal for the data channel bypass for external rf amp applications data channel digital pll provides flexible control of center frequency to support improved access times channel quality provided for parametric calibration channel data rates up to 210 mbits/sec. flexible and error-tolerant channel sync mark windowing scp (servo control processor) includes a servo control processor for focus, tracking, sled, and spindle servo loops significantly faster capture for focus and tracking effective in a wide range of parameter variations superior response to defects, shock, and vibration supports both clv (constant linear velocity) and cav (constant angular velocity) modes ecc real-time dvd ecc error correction real-time cd-rom layered ecc error correction with programmable number of sets of p-word and q-word corrections per sector (up to 64 total) c1/c2 ecc and de-interleaving real-time subcode error correction in cd-da (compact disc digital audio) mode decoder supports hardware streaming operation dvd navigation support supports adb (audio data buffering) automatic target sector header search hardware sector header validity check supports high-speed intel ? - and motorola ? -type microcontrollers supports nonmultiplexed and multiplexed address and data buses host interface true real-time hardware/software atapi compatibility supports ultra dma: capable of synchronous dma data rates up to 33.3 mbytes/sec. supports ata pio modes 3 and 4 transfers without iochrdy host interface (cont.) supports dma modes 1 and 2 hardware implementation of: - atapi packet command - atapi reset command high-performance pio/dma atapi bus transfer rate: - pio modes 3 and 4, multiword dma modes 1 and 2, and singleword dma modes 1 and 2 data transfer rate: - cd-rom clv ?maximum 32 data rate with 25% overspeed capture - cd-rom cav ? maximum 40 od data rate - dvd-rom clv ? maximum 6 data rate with 33% overspeed capture - dvd-rom cav ? maximum 8 od data rate - dvd+r clv ? max. 4x read buffer bandwidth: - 55 mbytes per second with 16-bit dram buffer manager dual-port circular buffer control with access-priority resolver supports streaming operation direct addressing of up to 4 mbytes of dram supports variable buffer segmentation programmable timing control for sdram host overrun control supports 16-bit sdram the CL-CS3712 servo control processor implements the focus, tracking, sled, and spindle servo loops. an adc is provided to convert the focus and tracking error signal. the outputs to the power drivers are linear dacs. the CL-CS3712 supports real-time dvd ecc, cd-rom c1/c2, and layered ecc correction, which is programmable for up to 64 p- and q-word corrections per sector. it also supports subcode r/w correction in cd- da (compact disc digital audio) mode. the buffer manager controls the flow of data from the data channel, through the ecc, and to either the host interface or the serial audio channel. data is stored and retrieved in the external buffer memory using interleaved access cycles. the buffer memory is implemented with sdram devices. up to 4 mbytes of sdram can be directly addressed by the CL-CS3712.
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com features (cont.) overview (cont.) microcontroller interface supports high-speed intel ? - and motorola ? -type microcontrollers supports nonmultiplexed and multiplexed address and data busses interrupt or polled microcontroller interface microcontroller access to six external switch settings on the buffer bus - three-level power-down capability when idle, automatic power-up when command is received
table of contents ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com iii system block diagrams .......................................................................................................... ...............1 dvd-rom ...................................................................................................................1 dvd player ..............................................................................................................1 functional decriptions......................................................................................................... ...................2 decoder ........................................................................................................................ .............2 dvd mode ....................................................................................................................2 cd form .......................................................................................................................3 data channel ................................................................................................................... .........4 servo channel.................................................................................................................. .........6 pickup/sensor interface ...............................................................................................6 servo control processor ..............................................................................................6 servo dacs..................................................................................................................6 register map ................................................................................................................... .......................8 pinout information ............................................................................................................ ...................13 pinout diagram ................................................................................................................ .......13 pin decriptions ................................................................................................................ ........14 package and order information.................................................................................................. .........19 package information ............................................................................................................ ...19 lqfp ordering information .....................................................................................................2 1
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. system block diagrams p reliminary d raft www.cirrus.com 1 system block diagrams dvd-rom dvd player buffer memory rom mc spindle sled/track/focus power drivers CL-CS3712 data channel rf amp servo control processor dvd/cd-rom ecc css atapi 3 host interface atapi decoder buffer memory rom mc spindle sled/track/focus power drivers CL-CS3712 data channel rf amp servo control processor dvd/cd-rom ecc css atapi 3 rom mc ir sensor user control led display ac-3 audio decoder mpeg2 video decoder 6 channel audio ntsc/pal encoder buffer memory (2 mbytes) 6 decoder
functional decriptions ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 2 functional decriptions this section overviews the main functional blocks of the CL-CS3712 integrated avi/ atapi dvd drive manager, and is divided into the following sub-sections: "decoder" on page 2 "data channel" on page 4 "servo channel" on page 6 decoder the CL-CS3712 contains a highly automated dvd/cd decoder that takes efm data from the analog front and digital prml read channel and transform this data through a series of operations into user data and sends it to the host controller. the sequence of operation is as follows: the high level firmware sets up the decoder through the up control interface. the decoder is controlled through a register set. the high level fw sets up the mode of operation (cd or dvd), the buffer manager and the host interface. the external sdram buffer is controlled through a set of address pointers programmed by the fw. this address pointers controls the data flow from the disc, to and fro to the ecc block and the host. dvd mode the actual data that is written on the dvd disc is a transformed version of the user data and follows the dvd physical specification. to understand the decoder flow the transformation process needs to be understood, which is beyond the scope of this document. in summary the user data is organized in sectors (2048 bytes). the transformation process involves adding id (sector #) and other information such as copy protection etc. to the data, scrambling the data, ecc encoding, splitting the data into recording frames , efm modulation and creation of efmp frames with unique sync patterns inserted for efmp frame identification. the function of the decoder is to take this transformed data and convert back into the user format. once the fw sets the start transfer control bit(s) in the decoder, the decoder starts processing the data from the read channel. the data is in the efmp format (eight to fourteen modulation plus) as defined in the dvd physical specification. the first step is to synchronize and align the data on the efmp frame boundaries by detecting unique sync patterns that are embedded in the efmp data stream. once the data is aligned on the efmp frame boundary it is de-serialized into 16-bit symbols, and than demodulated into 8 bits of data according to the efmp modulation standard. the next step is to determine the right starting point to start the transfer of data into the buffer. the fw will program the target header or id information. once the incoming data id matches the programmed id, data transfer to the buffer starts. the data transfer
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. functional decriptions p reliminary d raft www.cirrus.com 3 always start on an ecc boundary. the hw monitors the subsequent id to detect any interruption in the dvd data stream. after sufficient data is stored (at least 1 ecc block = 16 sectors) in the buffer, the error correction (ecc) system can start the error detection and correction. the error correction algorithm is programmable to allow for multi-pass correction, depending upon the application e.g. in the dvd-rom case, one would program it with more passes than for dvd-movie case. once ecc system has corrected one ecc block, this data can be transferred to the host. however before transferring this data need to be de-scrambled. the de- scrambling process is done during host transfer to save buffer bw. all the disc transfer, ecc correction, descrambling and host transfers are done in parallel without any intervention from the micro-controller. the hardware keeps track of how many sectors are transferred from the disc to the buffer, how many sectors have been corrected and how many transferred to the host. this is a fully automated operation also known as "full streaming". cd form the actual data that is written on the cd disc is a transformed version of the user data and follows the cd physical specification. the physical format of a cd disc is defined by the cd-digital audio physical specification. all cd whether cd-rom or cd-audio follows this standard. the recordable formats also follow this format, except for the linking area for multi-session recordings. again it is beyond the scope of this document to describe the cd formats as unlike the dvd format, there are host of different formats that the decoder needs to process. these are cd-da, cd-rom mode 0, cd-rom mode 2/form1 cd-rom mode 2/ form 2 plus cd-recordable data. in addition for the cd-da mode the decoder needs to process the sub channel data. the sub-channel contains additional information that is embedded in the efm data stream, which contains sector identifications and other information unique to the data. basically there are two types of data, cd-audio and cd-rom (with different modes and form). for cd-audio both the main channel and the sub channel data needs to be processed, for the cd-rom case only the main channel data is processed. the data arriving from the read channel is in the efm format, first it is synchronized and aligned on the efm frame boundaries. after synchronization the data is demodulated using the efm demodulation table. cd data is protected through 2 levels of correction c1 and c2 for the cd-da and 3 levels c1, c2 and c3 for cd-rom formats. c1 and c2 correction is done on the fly, i.e. before the data is transferred to the buffer. after efm demodulation, the data is sent to circ block (cross interleaved reed solomon code) which performs c1 and c2 correction on the incoming data. it also marks data it cannot correct, these markers called c2 pointers are used by the audio interpolator block to perform audio interpolation and in the case of cd-rom data, help the c3 correction engine in identifying the errors quickly. after the efm demodulation, the target header search looks for the target sector id in the data stream. in the case of cd-da this id is in the sub channel data stream,
functional decriptions ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 4 whereas in the case of cd-rom data it is embedded in the main channel data. once the target header is found the data transfer to the buffer starts and the de-scrambling is done while storing the data in the buffer from the disc. this data is than transferred to the host (atapi or audio dac interface) in the case of cd-rom data, depending on the format additional c3 correction needs to be performed. this flow is similar to the dvd case, i.e. when sufficient sectors are available in the buffer, the ecc engine starts correcting the data and the host transfer starts as soon as sufficient sectors are available after c3 correction. data channel the CL-CS3712 contains a partial response maximum likelihood (prml) read channel. the channel takes the analog signals from the optical pickup's (opu) photo detector outputs, detects the efm or efm+ data, and sends the data to the decoder. figure 1 illustrates the data channel architecture. figure 1. data channel diagram lpf rf adc equalizer digital vga gain offset defect rf track channel dac sequence detector control control detect crossing quality pd a pd b pd c pd d attenuator envelope detect + dac offset control offset control and summation itr to decoder
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. functional decriptions p reliminary d raft www.cirrus.com 5 the CL-CS3712 data channel architecture minimizes analog signal processing and migrates all feasible functionality to real-time digital signal processing blocks. the analog blocks are: summation amplifier digitally controlled variable gain amplifier (vga) analog low pass filter (lpf) analog-to-digital converter (rf adc) the main data path digital blocks are: digital equalizer interpolate timing recovery (itr) sequence detector the data path blocks are supported by the loop control blocks: the digital automatic gain control (dagc), offset control, and digital asymmetry control. the digital defect detect block allows the loops and the servo processor to coast through defects. u-controller accessible channel quality metrics support servo error signal gain and offset calibration. the attenuator and summation block interfaces the opu's a, b, c, and d photodetector outputs or the rf signal to the data channel. the attenuator and offset loop keeps the signals within the linear range of the circuitry. the channel can use either internally or externally summed rf. the variable gain amplifier (vga) is part of the automatic gain control (agc) loop. this amplifier's gain is exponentially proportional to its gain control. the analog low pass filter is designed to limit noise and serve as an anti-aliasing filter. the CL-CS3712 contains a high speed analog to digtial convertor that allows the majority of the signal processing to be performed in the digital domain. the sampling frequency is fixed and can be fsynth/2 or fsynth/4. this allows for a wide range of allowable input data rates. the digital equalizer is a 5 tap finite impulse response filter. it's coefficients change automatically as the data rate changes. the envelope detector is used to generate error signals for the offset and agc loops. the defect detection is also performed here. the digital offset loop keeps the read signal's baseline at the adc's range center. the agc also keeps the signal's amplitude within the adc's range. these loops are digital with the exception of the digital to analog convertors (dacs), adc, an adder, and a vga. the CL-CS3712 data channel performs data separation via the itr. this all digital implementation of a phase locked-loop (pll) makes for consistent chip to chip performance. it also allows for wide capture ranges. this decreases the speed of seeks in constant linear velocity (clv) mode. it has been designed handle the rate changes inherent in constant angular velocity (cav) mode automatically. asymmetry compensation is performed at the itr input. the CL-CS3712 contains a maximum likelihood sequence detector especially designed for low resolution dvd signals. this sequence detector achieves substantial signal processing gain over a slicer detector.
functional decriptions ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 6 the channel is controlled by a state machine that automatically starts timing recovery and deals with defects. this ensures quick recovery from defects and fast data acquisition after seeks. the CL-CS3712 contains a versatile digital block that can be used to monitor the ongoing ?health? or ?quality? of the channel, and that enables accurate equalization calibration to compensate for wide variations in disc resolution. servo channel the CL-CS3712 contains an integrated servo system that can control either a cdrom or a dvd mechanism, with the following features: servo control processor (scp), implementing algorithms designed specifically for optical disc drives supports dual pick up for cd and dvd applications integrated rf amplifier with laser diode automatic power control (ld apc) track counter with velocity estimation multi-function register banks external microcontroller interface circuitry programmable sample rate subsystem figure 2 shows the CL-CS3712 in a complete servo system. four control loops can be processed by this chip: focus, track, sled, spindle. since the CL-CS3712 contains a processor, control algorithms and interface circuitry, little external hardware and little microcontroller intervention is required to implement the servo system. pickup/sensor interface the pickup interface is the input to the servo control processor (scp). this circuitry provides the analog and digital processing needed before the scp can process the control signals from the sensors. since laser diode automatic power control and reference voltage generation are also provided, the CL-CS3712 can be connected directly to the pick up electronics without the need for an external rf amplifier. servo control processor the scp does all the processing necessary to control all four servo loops with little loading of the external microcontroller. the microcontroller sends setup information and commands to the control system through the microcontroller interface. it can also monitor key metrics and change control variables to optimize system performance. all parameter variables and scp instructions are stored in internal ram. since the cl- cs3712 is a ram based device, the microcontroller must first initialize these rams before servo operations can begin. servo dacs control outputs for the sled, focus, and track loops are converted to analog through an array of three 11-bit dacs. the spindle loop has a pulse width modulated (pwm) output.
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. functional decriptions p reliminary d raft www.cirrus.com 7 figure 2. servo system diagram microcontroller interface pick up interface servo control processor servo dacs microcontroller pick up electronics spin transducer spindle motor sled motor focus actuator tr a c k i n g actuator motion servo system 10 pd outputs vref1 ld-mon1 ld-pc1 ld-mon2 ld-pc2 dac outputs vref2 pwm-sp 4 power amps (scp)
register map ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 8 register map table 1: CL-CS3712 registers address (hex) register name r/w 00h atapi error (aterr) r/w 01h atapi features (atfea) r/w 02h atapi interrupt reason (atint) r/w 03h ata sector number (atsecn) r/w 04h atapi byte count low (atbcl) r/w 05h atapi byte count high (atbch) r/w 06h atapi drive select (atdsel) r/w 07h atapi command (atcmd) r 08h atapi packet (atpkt) r 09h alternate atapi error (alterr) r/w 0ah ata drive control/status (atdrv) r/w 0bh host drive address (hda) r/w 0ch at control 1 (atctrl1) r/w 0dh at control 2 (atctrl2) r/w 0eh at control 3 (atctrl3) r/w 10h host interrupt status 1 (hist1) r/w 11h host interrupt enable 1 (hien1) r/w 12h host interrupt status 2 (hist2) r/w 13h host interrupt enable 2 (hien2) r/w 15h pc mode control 1 (pcmode1) r/w 16h host transfer/packet fifo control (hxfr) r/w 17h atapi phase lock release (atulock) w 18h synchronous dma control (sdma) r/w 19h pc mode control 2 (pcmode2) r/w 1bh mpeg interface configuration 1 (mpegcfg1) r/w 1ch mpeg interface configuration 2 (mpegcfg2) r/w 1dh mpeg interface configuration 3 (mpegcfg3) r/w 1eh mpeg/bca interface interrupt status (mpegist) r/w 1fh mpeg/bca interface interrupt enable (mpegien) r/w 2ch c2p threshold control (c2ptc) r/w 2dh c2p threshold counter r/w 2eh servo coefficient control r/w 2fh dac interface status/control (dacs) r/w 30h-31h audio address pointer (aap) r/w 34h-35h host address pointer (hap) r/w
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. register map p reliminary d raft www.cirrus.com 9 38h-39h host buffer start address (hbsa) r/w 3ch-3dh local address base pointer (labp) r/w 40h-41h host buffer end address (hbea) r/w 44h-45h host transfer count (htc) r/w 46h scheduled buffer data access (sbda) r/w 47h buffer transfer control (btc) r/w 48h-49h adjust difference block count (adbc) r/w 4ah host transfer sector type (htst) r/w 4bh host transfer format 1 (htf1) r/w 4ch host transfer format 2 (htf2) r/w 4dh buffer timing control (btim) r/w 4eh buffer mode control (bmc) r/w 4fh dram refresh period (rfsh) r/w 50h-51h disc address pointer (dap) r/w 54h-55h disc buffer start address (dbsa) r/w 58h-5bh disc transfer count (dtc) r/w 5ch-5dh disc buffer end address (dbea) r/w 60h-61h corrector address pointer (cap) r/w 64h-65h sector to be corrected (stc) r/w 66h-67h current host transfer count (chtc) r 68h-6bh corrector transfer count (ctc) r/w 70h-71h buffer sector size (bss) r/w 72h-73h difference block count (dbc) r/w 74h-77h local address offset pointer (laop) r/w 78h-79h navigation pack address pointer (nap) r 7ah-7bh navigation pack detected (navpkdet) r 7ch navigation play control (navctl) r/w 7fh threshold transfer count (ttc) r/w 80h decoder operation mode (dopmd) r/w 81h disc configuration (dcfg) r/w 82h disc transfer control/status (dctrl) r/w 83h ecc control/status 1 (ecc1) r/w 84h dvd ecc error information (ecc2) r/w 85h data channel interface configuration 2 (dccfg2) r/w 86h target header (trghd) r/w 87h target header search time-out (hsto) r/w 88h raw header/subheader read-out (rhdrd) r 89h raw header mismatch threshold (rhdmth) r/w 8bh expected header read-out (exphd) r table 1: CL-CS3712 registers address (hex) register name r/w
register map ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 10 8ch raw header/subheader flag (hdflg) r 8dh header read-out control (rdctrl) r/w 8eh data channel interface configuration 3 (dccfg3) r/w 90h disc interrupt status 1 (dist1) r/w 91h disc interrupt enable 1 (dien1) r/w 92h disc interrupt status 2 (dist2) r/w 93h disc interrupt enable 2 (dien2) r/w 94h disc transfer control 1 (dctrl1) r/w 95h sector per track count (sptc) r/w 98h bca control 1 r/w 99h bca status 1 r/w 9ah bca control 2 r/w 9bh bca control 3 r/w 9ch bca control 4 r/w 9dh bca channel clock r/w 9eh-9fh spindle speed r a0h defect address fifo1/fifo2(dmf) r/w a1h c1/c2 control (c12cntl) r/w a2h efm sync control (efmsyctl) r/w a3h efm plus sync control (efmpsyctl) r/w a4h subcode read-out (sbrd) r a5h subcode control/status (sbctl) r/w a6h efm plus sync status (efmpsynsts) r a7h corrected id read-out (cidr) r/w b5h sram diagnostics status 1 (sramst1) r b6h sram diagnostics status 2 (sramst2) r b7h sram diagnostics status 3 (sramst3) r b8h sram diagnostics control 1 (sramdiactl1) r/w b9h sram diagnostics control 2 (sramdiactl2) r/w bah sram uc access data (sramupdata) r/w bbh sram uc access address (sramupaddr) r/w bdh test1 (test) r/w beh product and revision number (prvn) r bfh miscellaneous control (misc) r/w c0h power control r/w c1h clock selection r/w c2h rf adc diagnostic control 1 r/w c3h rf adc diagnostic control 2 r/w c4h analog diagnostic r/w table 1: CL-CS3712 registers address (hex) register name r/w
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. register map p reliminary d raft www.cirrus.com 11 c5h-c7h rf adc diagnostic accumulator r c8h laser diode 1 control r/w c9h laser diode 2 control r/w cah reference voltage/diode/rf amp configuration r/w cbh pickup interface r/w cch analog static data channel vga r/w cdh analog static data channel lpf r/w ceh rf adc calibration control r/w cfh bandgap reference calibration control r/w d0h moving-average filter/digital filtering 1 r/w d1h digital filtering 2 r/w d2h zone control r/w d3h offset loop control r/w d4h automatic gain control r/w d5h gain loop accumulator layer 0 and layer 1 r/w d7h offset loop accumulator layer 0 and layer 1 r/w d8h rf envelope detector read r/w d9h lf envelope detector r/w dah topstate monitor r/w dbh asymmetry accumulator layer 0 and layer 1 r/w dch asymmetry control r/w ddh channel top level state control 1 r/w deh channel top level state control 2 r/w dfh channel top level state control 3 r/w e0h dpll control 1 r/w e1h dpll control 2 r/w e2h dpll control 3 r/w e3h sequence detector r/w e4h-e5h dpll center period accumulator r/w e6h-e7h channel quality accumulator r e8h channel quality mode select r/w e9h defect control 1 r/w eah defect control 2 r/w ebh defect control 3 r/w ech rf bca slicer r/w edh rf bca parser r/w efh digital diagnostic r/w f0h track crossing control r/w f1h servo control r/w table 1: CL-CS3712 registers address (hex) register name r/w
register map ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 12 f2h scp program command (spc) r/w fbh scp state generator m divider r/w fch scp state generator n/p dividers r/w fdh memory data r/w feh-ffh scp memory control/address r/w table 1: CL-CS3712 registers address (hex) register name r/w
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. pinout information p reliminary d raft www.cirrus.com 13 pinout information pinout diagram agnd nc_gnd agnd rext avdd nc_gnd ld-mon2 ld-pc2 vref1 agnd avdd pd-cf hp_filt2 rf_n rf_p pd-cb pd-ca pd-ce pd-cc pd-cd nc_gnd pd-t hp_filt3 pd-db pd-dd pd-dc pd-da hp_filt1 ld-mon1 ld-pc1 pd-df2 pd-df1 pd-de2 pd-de1 agnd avdd apc_gnd dac-f dac-t adc-aux avdd vref2 nc_gnd dac-sl dac-tl nc_gnd avdd nc_gnd agnd pwm-sp spin_p spin_n 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CL-CS3712 208-pin lqfp 105 107 106 108 109 110 112 111 113 114 115 117 116 118 119 120 122 121 123 124 125 127 126 128 129 130 132 131 133 134 135 137 136 138 139 140 142 141 143 144 145 146 147 148 149 151 150 152 153 154 156 155 157 159 158 160 161 162 164 163 165 166 167 169 168 170 171 172 174 173 175 176 177 179 178 180 181 182 184 183 185 186 187 189 188 190 191 192 194 193 195 196 197 198 199 200 201 203 202 204 205 206 208 207 nc nc nc nc nc av dd xtalo mclk2/xtali agnd bgnd mclk1 clk_out uc_clk cgnd dma33clk rst* int1 int2 bgnd cs* wr*/r/w* rd*/ds a7/ale a6 a5 a4 bvdd a3 cgnd a2 a1 a0 cvdd ad7 bgnd ad6 ad5 ad4 ad3 ad2 ad1 ad0 ef2 bvdd ef1 bgnd n/c n/c extcr n/c test test_enbl* ba2 ba1 ba0 bgnd hreset* dd7 cgnd dd8 cvdd dd6 dd9 bgnd dd5 bvdd dd10 dd4 dd11 dd3 dd12 dd2 bvdd dd13 bgnd dd1 dd14 dd0 dd15 dmarq diow* dior* iordy bgnd dmack* bvdd intrq iocs16* da1 pdiag* bvdd da0 bgnd da2 cs1fx* cs3fx* cgnd dasp* cvdd n/c n/c extcq n/c bgnd diag4 diag3 diag2 diag1 rf_env ch qual mon agnd avdd bgnd sdclk cke dqmu dqml bgnd we* bvdd cs0* cs1* cas* ras* bd15 bd14 bd13 bd12 bvdd cvdd bd11 cgnd bd10 bd9/pll_clk_bp_sl bd8/cs_polarity bd7/mot-i* bd6/m-nm* bd5/dec_clk_bp_sl bd4/dtsl bd3/xtsl bgnd bd2/ucsl2 bvdd bd1/ucsl1 bd0/ucsl0 ba11 ba10 ba9 ba8 ba7 ba6 ba5 bgnd ba4 bvdd ba3
pinout information ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 14 pin decriptions table 2: pin map legend abbreviation or convention description i a pin that functions as an input only. o a pin that functions as an output only. i/o a pin that operates as an input or an output. od an open-drain output. ts a test pin. z a tristate output or input/output. (*) following a signal name designates an active-low signal. pin name in italics an italicized function name for a multifunction pin indicates that the function is only valid on the low-to-high transition of rst*. table 3: CL-CS3712 pin map type name pin(s) i/o function host interface signals dd15 dd14 dd13 dd12 dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 79 77 74 71 69 67 63 60 58 62 65 68 70 72 76 78 i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts i/o-ts host data bus da2 da1 da0 94 89 92 i i i host address lines cs1fx* 95 i host chip select 0* cs3fx* 96 i host chip select 1* dior* 82 i host i/o read strobe* diow* 81 i host i/o write strobe* hreset* 57 i host reset* iocs16* 88 od 16-bit data transfer* intrq 87 o -ts host interrupt request iordy 83 o -ts i/o channel ready
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. pinout information p reliminary d raft www.cirrus.com 15 host interface signals (cont.) dmarq 80 o -ts dma request dmack* 85 i dma acknowledge* pdiag* 90 i/o passed diagnostics* dasp* 98 i/o slave present buffer interface signals sdclk 10 o sdram clk cke 11 o clock enable dqmu 12 o upper data mask enable dqml 13 o lower data mask enable we* 15 o write enable cs0* 17 o chip select 0 cs1* 18 o chip select 1 cas* 19 o column address strobe low ras* 20 o row address strobe ba11 ba10 ba9 ba8 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 42 43 44 45 46 47 48 50 52 53 54 55 o o o o o o o o o o o o buffer address [11:0] bd15 bd14 bd13 bd12 bd11 bd10 21 22 23 24 27 29 i/o i/o i/o i/o i/o i/o buffer data bus bd9/ pll_clk_bp_sl 30 i/o buffer data bus bit 9 / pll clock bypass bd8/ cs_polarity 31 i/o buffer data bus bit 8 / ucomputer clock select bd7/ mot-i* 32 i/o buffer data bus bit 7 / motorola-intel bd6/ m-nm* 33 i/o buffer data bus bit 6 / multiplexed - nonmultiplexed bd5/ dec_clk_bp_sl 34 i/o buffer data bus bit 5 / decoder clock bd4/ dtsl 35 i/o buffer data bus bit 4 / drive test select bd3/ xtsl 36 i/o buffer data bus bit3 / xtal select bd2/ ucsl2 bd1/ ucsl1 bd0/ ucsl0 38 40 41 i/o buffer data bus bit 2-0 / ucomputer clock select table 3: CL-CS3712 pin map (continued) type name pin(s) i/o function
pinout information ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 16 microcontroller interface signals ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 123 121 120 119 118 117 116 115 i/o i/o i/o i/o i/o i/o i/o i/o local microcontroller address and data bus a7/ale 134 i local microcontroller address bus bit 5 / address latch enable a6 a5 a4 a3 a2 a1 a0 133 132 131 129 127 126 125 i i i i i i i local microcontroller address bus cs* 137 i chip select* rd*/ds 135 i read strobe*/data strobe wr*/ r/w* 136 i write strobe/ read/write* int1 140 o-od interrupt1 int2 139 o-od interrupt2 rst* 141 i reset* servo analog interface signals spin_p spin_n 158 157 i i spin transducer dac-tl 164 o tilt dac dac-sl 165 o sled dac dac-f 171 o focus dac dac-t 170 o tracking dac adc-aux 169 i auxiliary adc pwm-sp 159 o spin pwm extcr 108 i external track counter real and external track counter quadrature extcq 102 i vref2 167 o voltage reference 2 clock interface signals mclk1 146 i master clock 1 mclk2/xtali 149 i master clock 2 / crystal input xtalo 150 o crystal output dma33clk 142 i dma33 clock clk_out 145 o clock output uc_clk 144 o microcontroller clock table 3: CL-CS3712 pin map (continued) type name pin(s) i/o function
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. pinout information p reliminary d raft www.cirrus.com 17 rf amplifier interface signals pd-de1 pd-de2 pd-df1 pd-df2 175 176 177 178 i i i i servo differential push pull amp inputs pd-da pd-dc pd-dd pd-db 182 183 184 185 i i i i photo detector-dvd rf_p rf_n 194 195 i i rf external summation inputs pd-ca pd-cb pd-cc pd-cd 192 193 190 189 i i i i photo detector-cdrom pd-ce pd-cf 191 197 i i photo detector e & f-cdrom pd-t 187 i photo detector-t ld-pc1 ld-pc2 179 201 o o laser diode power control ld-mon1 ld-mon2 180 202 i i laser diode monitor vref1 200 i/o voltage reference 1 rext 205 i/o external resistor hp_filt1 hp_filt2 hp_filt3 181 196 186 i i i high pass filter diagnostic signals diag1 diag2 diag3 diag4 4 3 2 1 i/o i/o i/o i/o diagnostic 1-4 rf_env 5 o rf envelope ch qual mon 6 o channel quality monitor ef2 ef1 114 112 o o error flag (2:1) test_enbl* 105 i test enable test 106 i test table 3: CL-CS3712 pin map (continued) type name pin(s) i/o function
pinout information ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 18 power and ground pins avdd 8 , 151, 162, 168, 173, 198, 204 ? analog power supply agnd 7, 148, 160, 174, 199, 206, 208 ? analog ground bvdd 16, 25, 39, 51, 66, 73, 86, 91, 113, 130 ? buffer power supply bgnd 9, 14, 37, 49, 56, 64, 75, 84, 93, 104, 111, 122, 138, 147 ? buffer ground cvdd 26 , 61 , 99, 124 ? core power supply cgnd 28, 59, 97, 128, 143 ? core ground apc_gnd 172 ? apc ground nc_gnd 161, 163, 166, 188, 203, 207 ? nc ground table 3: CL-CS3712 pin map (continued) type name pin(s) i/o function
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. package and order information p reliminary d raft www.cirrus.com 19 package and order information package information for complete dimensional and thermal information, see the latest version of the cirrus logic package information guide . the package and pcb design affects the amount of power that can be dissipated by the package and could limit the maximum transfer rate. note: dimensions are in millimeters (inches), and controlling dimension is millimeter. drawing above does not reflect exact package pin count. before beginning any new design with this device, please contact cirrus logic for the latest package information. pin 1 indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) bsc 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0 min 7 max 0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 0.45 (0.018) 0.75 (0.030) 0.05 (0.002) 1.00 (0.039) bsc pin 1 pin 208 1.60 (0.063) 0.15 (0.006) CL-CS3712 208-pin lqfp
package and order information ds588pp1 - rev 0.4 april 11, 2002 c onfidential copyright ? 2002 cirrus logic inc. p reliminary d raft www.cirrus.com 20 CL-CS3712 208-pin epad
c onfidential ds588pp1 - rev 0.4 april 11, 2002 copyright ? 2002 cirrus logic inc. package and order information p reliminary d raft www.cirrus.com 21 lqfp ordering information ? 33 qc ? a cirrus logic, inc. mass storage part number data rate: package type: lqfp = q temperature range: revision c = commercial mb/s CL-CS3712 ? copyright, cirrus logic inc., 2002 preliminary product information describes products that are in production, but for which full characterization data is not yet available. cirrus logic in c has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the informat ion is subject to chang e without notice. no responsibility is assumed by cirrus logic inc. for the use of this information, nor for infringements of pat ents or other rights of thir d parties. this document is the property of cirrus logic inc. and implies no license under patents, copyrights, or trade secrets. cirrus logic and log o are trademarks of cirrus logic, inc. other trademarks in this document belong to their respective companies. cirrus logic inc. p roducts are covere d by the following u.s. patents: 4,293,783; re. 31,287; 4,763,332; 4,777,635; 4,839,896; 4,931,946; 4,975,828; 4,979,173; 5,032,9 81; 5,122,78 3 5,131,015; 5,140,595; 5,157,618; 5,179,292; 5,185,602; 5,220,295; 5,280,488; 5,287,241; 5,291,499; 5,293,159; 5,293,474; 5,297, 184; 5,298,91 5 5,300,835; 5,311,460; 5,313,224; 5,327,128; 5,329,554; 5,351,231; 5,359,631. additional patents pending.

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